ECP5-PCIe: A PCIe interface written in nMigen for the ECP5 FPGA

Posts

Sep 23, 2020
Development Report
Sep 3, 2020
DLLP transmitter
Aug 28, 2020
SERDES compiled with diamond and channel and DCU can now be configured via parameters.
Aug 25, 2020
DLLP receiver and CRC implemented
Aug 21, 2020
LTSSM working well, getting DLLPs
Aug 19, 2020
LTSSM working to L0, scrambling implemented
Aug 14, 2020
Serdes gearing broken; Soft gearing as a fix
Aug 10, 2020
Fixed PHY cdc, now working fine a significant portion of the time
Aug 6, 2020
Some fixes for the PHY
Jul 31, 2020
Some changes to the SERDES and a new SKP sequence transmitter
Jul 30, 2020
SERDES testing finished
Jul 26, 2020
Weekly Jul-4
Jul 25, 2020
ROCKPro64 automatic PCIe init
Jul 22, 2020
Testing the serdes - Undecoded
Jul 20, 2020
ROCKPro64 UART control
Jul 16, 2020
Weekly Jul-3
Jul 16, 2020
Testing the SERDES
Jul 11, 2020
Weekly Jul-2
Jul 9, 2020
Serdes and Domain Crossing tests
Jul 1, 2020
Weekly Jul-1
Jul 1, 2020
Further work on the LTSSM and further reading of documentations
Jun 26, 2020
More comments and LTSSM bugfixes and more debug options
Jun 24, 2020
TX and RX+TX test cases working
Jun 23, 2020
Weekly Jun-3
Jun 21, 2020
LTSSM now fully in RX clock domain
Jun 20, 2020
Test cases for RX and TX, comments and code formatting
Jun 16, 2020
Further work on the LTSSM state machine
Jun 15, 2020
Weekly Jun-2
Jun 13, 2020
RX, TX, LTSSM state machines
Jun 12, 2020
RX, TX, LTSSM state machines
Jun 8, 2020
x2 Gearing working, TS1/2, SKP testing state machine implemented
Jun 7, 2020
Yumewatari commit f61133d working in nMigen!
Jun 7, 2020
Weekly Jun-1
Jun 6, 2020
Yumewatari commit f61133d working!
Jun 4, 2020
UART Debugger
Jun 3, 2020
SERDES Progress
Jun 1, 2020
Progress until now
May 16, 2020
What was done until now?
May 16, 2020
Introduction to ECP5-PCIe